In this paper, a noise and power-optimized fully-differential capacitive feedback CMOS preamplifier circuit is designed using a commercial 0.35 μm CMOS technology node. The designed preamplifier circuit is part of an analog front-end SoC, which monitors the human electrocardiogram (ECG) using dry electrodes. The transistors in the interface circuit are biased in weak inversion region for lower total input referred noise and power dissipation respectively. With an input referred noise of 14.5 μ V RMS and 2.55 μW power dissipation, the resultant preamplifier achieves a gain of 52dB over a bandwidth range of 0.003 Hz to 880 Hz with Noise Efficiency Factor (NEF) of 2.52.