Fig.2. Active loop filter PLL system
While designing, if PFD frequency of PLL is large relative to loop bandwidth of loop filter there is more advantage in building higher order loop filter. Fig. 3 shows performance of phase noise, locking time and gain of active S-band PLL output that uses reference source (TCXO) of 100 MHz. There is a big challenge to develop a compact high frequency RF sources with better phase noise performance for airborne radar application. PLL based frequency multiplier technique is a good approach for meeting the critical requirements of airborne application. This approach makes use of multiplier IC’s for transforming lower frequency PLL output into higher frequency signals. Degraded phase noise performance is the shortcoming of frequency translation technique (from lower frequency to higher frequency).
VCO phase noise is dominant in the outside the loop bandwidth as can be seen in the Fig.3(i) and Fig.3(vi). Fig.3(ii) gives the voltage requirement (\(V_{\text{tune}}\)) of VCO for the frequency. Close loop bandwidth can be estimated from the Fig.3(v); it also gives the gain of the active loop filter to cover VCO range. Fig.3(iii) shows reference phase noise which is dominant within the loop bandwidth of the PLL. Fig.4(iv) shows the VCO sensitivity which can be seen as the constant for the \(V_{\text{tune}}\)voltage range which changes very less. Fig.3(vi) gives the combined effect of the phase noise for the PLL. Fig.3(vii) is then second order response of the system which shows the system is stable at the lock frequency 2.66GHz. Closer look can be taken for the frequency lock in Fig.3(viii) which takes 50us lock time.