Experiments and discussion: The device studied is the 100 V/25 mΩ Schottky-type p-GaN gate HEMTs commercial product. The device structure can be found in our previous report [7]. Fig. 1 (a) plots the SC measurement circuit. Fig.1 (b) shows the repetitive SC stress and device characterization strategy. The devices were stressed by up to 150 SC pulses that is 50% higher than our previous report [7], while the device characteristics were respectively recorded after the1st, 10th, 30th, 60th, 100th , and 150th SC pulse during the repetitive SC evolution. Fig. 2 plots the typical repetitive SC waveforms of V GS=6 V,V DD=70 V and T SC=10 μs for the 1st , 10th ,30th , 60th ,100th , and 150th SC cycle. Within each SC event, the decreased SC drain currentI D is a result of the significantly high SC current induced junction temperature T j increase [4] and the subsequent 2DEG mobility reduction [8]. In addition, the peak SC I D reduced from 55.2 to 45.1 A due to the positive shift of V th. Besides, the increasedT j may also result in gate leakage increase during the SC event [7], which leads to a higher voltage drop across the resistor (R G) connected to the gate terminal as shown in Fig. 1 (a). As a result, the SC waveform ofV GS exhibits a moderate decrease within a single SC event as can be seen in Fig. 2 (b). On the other hand, together with the evolution of the repetitive SC cycles, the consistent trap filling in the gate region results in suppressed gate leakage which leads to a reduced voltage across R G and then a higher effective gate bias is applied at the gate terminal of the device. Hence, the V GS at the end point of theV GS SC waveform exhibits a marginal increase (see Fig. 2 (b)). The repetitive SC experiments are conducted on DUT1, 2, 3 and 4 at V GS =6 V, T SC=10 μs, and varied V DD=40 V, 50 V, 60 V and 70 V, respectively. Fig.3 (a) shows the transfer curves of DUT4. It can be seen that the transfer characteristic exhibits a substantial positive shift which leads to the V th (defined atI DS=1 mA) significantly shifted from 1.22 V in the fresh device to 1.90 V after SC stress. Fig. 3 (b) plots the ΔV th of DUT 1~4 versus the SC cycles. The ΔV th increases with the increasing SC cycles and gradually saturates for SC cycles >120. Moreover, with the identical SC stress cycles, the device exhibits higher ΔV th stressed with higherV DD. Even though exhibiting substantialV th instability, all of the 4 tested devices were not failed after 150 SC cycles that suggests the strong repetitive SC capability of the devices, which is quite different from the reported 650 V Schottky p-GaN gate HEMTs featuring weak repetitive SC capability [4]. However, it should be pointed out that the significantly positive V TH shift may induce an insufficient turn-on of GaN HEMTs as well as additional turn-on loss, which is detrimental to achieve high power efficiency of GaN HEMTs particularly for the low voltage GaN HEMTs that is supposed to operate at higher frequency where the switching loss is crucial for the power circuits.
Fig.4 compares the typical gate leakage currentI GSS and off-state drain leakage currentI DSS of DUT-4 before and after SC stress.I GSS is measured with source/drain terminal grounded, while I DSS is measured in off-state with V GS=0 V. In positive gate bias, the applied voltage mainly drops across the upper metal/p-GaN Schottky diode in reverse mode, which facilitates blocking the gate leakage. In contrast, in negative gate bias, the upper Schottky diode is biased in forward mode that enables hole current conduction. Meanwhile, the applied gate voltage mainly drops across the p-i-n diode in reverse mode, which leads to higher reverse leakage by trap-state assistant electron tunneling due to the presence of trap states at p-GaN/AlGaN interface (e.g. N-vacancy or Ga-dangling bond) [9], [13] and in AlGaN barrier induced by Mg-dopant out-diffusion [10], [12]. Hence, the overall reverse gate leakage is higher than that in forward. Moreover, it can be seen that the I GSS exhibits a reduction after SC stress. Because the positive gate bias during the SC stress can sufficiently lower the p-GaN/AlGaN barrier, the significantly high SC current flows through the device with a large amount of 2DEG accumulated at the AlGaN/GaN interface channel. Meanwhile, the respectable large potential difference between gate and drain during SC event may result in a high electric-field located at the drain-side gate edge [4]. In this manner, driven by the locally high electric-field part of the high-density electrons in the channel can leap over the lowered energy barrier or tunneling through p-GaN/AlGaN gate stack, which leads to the increased gate leakage during the SC event and the simultaneous electron trapping by interface states at the p-GaN/AlGaN interface [11] and bulk traps in AlGaN barrier as depicted in Fig. 5. After occurrence of the electron-trapping, the interface states and bulk states filled with electrons are negatively charged, which tends to deplete the 2DEG in the channel and then results in positive shift inV th. The trap states are gradually filled along with the increasing SC cycles. Hence, the ΔV thincreases with the SC cycles and then exhibits a saturation trend as observed in Fig. 3. Besides, the negatively charged traps can effectively suppress the gate leakage after stress as observed in Fig. 4 (a). Fig. 4 (b) shows the drain leakage I DSS and gate leakage I G in off-state measured before and after SC stress of DUT4. The identical I DSS andI G suggests that the off-state leakage of the device is dominated by the drain-to-gate leakage. More importantly, similar to I GSS measured in Fig 4(a), the off-state I DSS as well asI G show an obvious reduction after SC stress as shown in Fig. 4 (b), which reinforces that the occurrence of electron trapping in the p-GaN gate stack rather than in GaN buffer beneath the 2DEG channel.