Energy-efficient switching method using input-swapping for high resolution SAR ADCs

S. Kocak ^1,2, T. Akin ^1,2

¹ Dept. of Electrical and Electronics Eng., METU, Ankara Turkey

² Mikro-Tasarim Elektronik Inc., Ankara, Turkey

Email: serhat.kocak@metu.edu.tr

Introduction: Successive approximation register (SAR) analog-to-digital converters (ADCs) have been widely used in recent years in many applications that require low-power consumption and medium resolution such as 10-bit. There is a constant effort in literature to lower the power consumption of the SAR ADCs even further while increasing their resolutions. A large portion of the power consumption in the SAR ADCs comes from the switching power of the DACs. Recent studies in the SAR ADCs have focused on the switching power reduction of the DACs with different methods [1‑6] compared to the conventional approach, but all of these methods have different drawbacks. The set-and-down switching method in [1] achieves 99.3% reduction in the average switching energy at the expense of large common-mode voltage variation that degrades the performance of the comparator, which is the main factor determining the resolution. The bi-directional switching method in [2] can provide higher resolution as it reduces the common-mode variations by using a single-side capacitor switching; however, this method consumes high reset energy, increasing the power consumption. The V _CM-based charge-recovery switching method in [3] eliminates the reset energy, but it needs extra voltage reference compared to the conventional switching method, which increases the power consumption and requires large silicon area due to the need for the increased number for unit capacitors compared to the state-of-the-art methods; the stability of this third reference voltage is also a concern for the high-resolution implementations in this method. The two-step switching method in [4] reduces the required number of unit capacitors significantly, reducing the area of the unit capacitors; however, this method increases the complexity of the DAC control logic due to the additional circuits, preventing its use in high resolution SAR ADCs. The merge and split switching method in [5] achieves great reduction in average switching energy by creating floating nodes instead of using a third reference voltage, but this approach can lead to linearity problems, limiting its use in high resolution SAR ADCs. The proposed method in [6] needs a very small number of unit capacitors and therefore reduces the switching energy by about 99.5% compared to conventional SAR ADCs. However, this method requires V _REFN, V _REFP, andV _CM to perform the conversion, and again the third reference voltage can seriously degrade the resolution performance of the ADCs. The proposed scheme in [7] divides the input differential voltage by 2 to reduce the power, but demands a better comparator to resolve small voltages, i.e., limiting the ADC resolution. Except the proposed methods in [3] [6], and [7], the above methods use top plate sampling which can degrade the linearity performance due to non-linear parasitic and non-linear clock feedthrough effects. There is a need for a new switching method for achieving high resolution and lower power SAR ADCs. This paper presents a novel switching method by using input swapping with bottom plate sampling and low common-mode variation. The proposed method achieves 93.7% reduction in switching energy and decreases the area by 75% compared to the conventional switching method used in conventional SAR ADCs with a typical 10-bit resolution, while allowing high resolution implementations such as 14 bits.

Fig. 1 shows the proposed 10-bit SAR ADC architecture, which employs a coarse and a fine comparator. Before starting the actual sampling on the main DAC array, first comparison is performed by the coarse comparator to determine whether the differential input is positive or negative. Depending on the result of this first comparison, the DAC arrays are connected to the input voltages, and actual sampling is initiated. At the same time, the output of the fine comparator is also adjusted according to the output of the first comparison. At the end of the sampling, 7 clock cycles are required for the conversion to determine remaining bits of the output. In addition, the proposed scheme split the MSB capacitor into binary-weighted sub-capacitors in the DAC array to remove the reset voltage.