Fig. 1. Proposed 10-bit
SAR ADC architecture
Proposed switching method: In the conventional switching method,
there are 2N+1 unit-capacitors, where N represents the
resolution; each of the capacitors, except the dummy capacitor, switches
to either V REFP or V REFN,requiring large amount of switching energy. In addition to switching
energy, reset energy is required to switch back the capacitors to
previous voltage in the intermediate cycles. As a result, the switching
energy is very large and wasted. The switching energy can be reduced
with the proposed method in this paper, by using either common-mode
voltage V CM or V REFN,
while V REFP is only used in the sampling process.
This method also reduces the total number unit capacitors to
2N-1. In addition, the number switches connected to
the bottom plate of each capacitor is also reduced compared to the
conventional switching method, which lowers the DAC control logic
complexity and decreases the settling time of each capacitor due to the
reduction in the switches.
Fig. 2 explains the proposed switching scheme for a sample 4-bit SAR
ADC. The proposed scheme starts the sampling phase in which the input
signal is sampled on the bottom plates of the capacitors, while the top
plates of all capacitors are connected to either VREF or
VCM. At the end of the sampling phase, the bottom plate
of the MSB capacitor, which is split into sub-capacitors, is connected
to VCM, while the bottom plates of the remaining
capacitors are connected to ground in the DACP array. In
contrast, in DACN the bottom plate of the MSB capacitor
is connected to ground while the bottom plates of the remaining
capacitors are connected to VCM. After the MSB
capacitors are settled to the required voltages, a comparison is
performed. If the differential input voltage is greater than
VCM, in the next conversion cycle, the bottom plates of
(MSB-1) capacitors are connected to VCM and ground. On
the other hand, if the differential input voltage is smaller than
VCM, the bottom plates of the largest capacitor in the
MSB capacitor returns to previous voltage and no changes occur at the
bottom plates of the (MSB-1) capacitor. The conversion continues until
the last conversion. In the last conversion, according to the result of
the previous conversion, one DAC does not change while the bottom plate
of the LSB capacitor in the other DAC is connected to either ground or
VCM. During the entire DAC switching, only
VCM and ground are used to perform the conversion. A
third reference voltage called as VREF is not used
during the entire switching steps. As a result, the precision of the
switching becomes better and does not depend on the accuracy of the
third reference voltage.