In this paper, we propose a PE-based parallelism configurable polar encoder hardware architecture for emerging high-speed 5G communication system. This encoder architecture is applied to the 5G-NR PBCH channel polar encoder, implemented with functional modules such as CRC generation and interleaving, channel encoding, and rate matching as specified in the 3GPP protocol. Next, based on the united power format (UPF) low-power management technology, the PBCH polar encoder architecture is divided into different power domains based on their operating characteristics to reduce the power consumption. Experimental results show that the proposed polar encoder achieves throughput up to 30 Gbps. Based on TSMC 40 nm CMOS technology, by applying the proposed low-power methodology, the power consumption of the PBCH polar encoder at parallelisms of 8, 16, and 32 are 1.236 mW, 1.170 mW, and 1.084 mW, achieving power reductions of 24%, 29%, and 35% when comparing to non-low-power design, respectively.