not-yet-known not-yet-known not-yet-known unknown A Memristor-controlled CMOS reconfigurable true time delay circuit is introduced in this paper. The delay circuit includes 3 stages of g m -C all pass filter delay elements connected in cascade, and memristor-based tuneable DC voltage sources. The memristor value variation changes the DC bias voltage inputs of the delay elements, and thus controls the delay time indirectly: The memristor resistance changes in analogue from 10kΩ to 17 kΩ , changing the tuneable DC voltage source output from 584mV to 711mV DC voltage and the delay from 269ps to 632ps. The delay circuit can work in a frequency range from 50MHz to 1.6GHz with gain ripple smaller than 3dB. The resolvable delay time step across the delay range is < 8.7ps, troughing at as low as 0.4ps. A delay circuit working in the MHz region is also designed to compare the performance with the GHz circuit, and a memristor programming circuit is built to change the resistance levels of memristors.

This article proposes a class of asymmetric 2 ×n resistor network model which contains multiple independent resistors, the study of asymmetric resistor network models is a challenge. We conducted in-depth research on this issue using the RT-V theory (Chinese Physics B, 2017, 26(9): 090503) and achieved new theoretical breakthroughs. This paper derived five original equivalent resistance formulae for this asymmetric 2 ×n circuit network, and also discusses the analytical expressions for equivalent resistance in different special cases, and several interesting results have been derived, indicating that the original resistance formula has powerful functionality. Finally, visual graphics of two types of equivalent resistances are provided using MATLAB drawing tools, which reveals the law of equivalent resistance changing with resistance variables. The research theory and technology in this article will provide a new theoretical basis for related scientific, engineering, and simulation research.

not-yet-known not-yet-known not-yet-known unknown A variable gain amplifier (VGA) is an essential building block used in the automatic gain control (AGC) loop to provide a continuous, adjustable gain for the signal strength. To maintain the stability and consistency of the AGC loop, it is necessary to ensure that the gain of the VGA has an accurate dB-linear characteristic. This tutorial provides a detailed overview of the development of dB-linear VGAs based on differential pair structures over recent years. We categorise various VGA cells based on differential pair structures, analyse their operating principles, and explain the key features of each topology. Based on observation and extraction of the dB-linear implementation schemes used by these VGAs, we summarise three basic methods for achieving dB-linear gain control. We also discuss specific methods for realising the exponential function, using a true exponential and a mathematical approximation, and present the different types of approximation functions adopted in the works described here. Considerations in regard to the tuning range, gain error, bandwidth, linearity, process-temperature robustness, and circuit simplicity are also discussed. Finally, we draw comparisons and give perspectives for future dB-linear VGAs.

This paper presents an AI-based framework designed for learning and regenerating analog circuits from academic papers. The framework comprises four distinct modules: circuit extractor, table extractor, text extractor, and simulation executor. The circuit extractor module utilizes deep learning object detection to identify devices and their associated textual descriptions while extracting interconnections between devices. The table extractor module handles textual and image-based tables, extracting device parameters and simulation data. The text extractor module leverages Optical Character Recognition (OCR) and AI models to extract supplementary information. The simulation executor employs this information to conduct simulations and optimize circuit performance. In our experiments, our method effectively extracts multimodal circuit design information, achieving an average accuracy of up to 97% in target detection within the circuit extractor module. The improved performance during the simulation process further validates the effectiveness of our framework.

In advanced processes, Single-Inductor Multiple-Output (SIMO) DC-DC converters with battery voltage as input face serious overvoltage problems due to low MOSFET withstand voltage. To meet the needs of SIMO converter design in advanced processes, this paper first proposes a SIMO converter with an adaptive power supply buffer (APSB) and voltage-limiting techniques in 22 nm CMOS. The proposed APSB technology ensures that the driving voltage of the power stage remains unchanged under the changing power supply, solving the breakdown problem caused by low MOSFET withstand voltage and simplifying the circuit design of the power stage. The proposed voltage-limiting techniques avoid the overvoltage of the internal circuit by special voltage-limiting design for the VX2 node and output voltage during startup and steady state. The proposed SIMO is designed and validated under a 22 nm CMOS process. The input power supply range is 2.8 V-5 V, and the three output voltages are 0.8 V, 1.1 V, and 1.8 V, respectively. The maximum load for each output voltage is 250 mA. The SIMO system achieves a peak efficiency of 92.2% over the full load range.

This article proposes a high step-up, low switching voltage stress DC-DC converter based on the traditional Boost circuit, incorporating switched-capacitor (SC) and coupled-inductor (CL) techniques. The design approach of this converter involves replacing the single switch in a single-switch DC-DC converter with SC, combining CL together, and integrating the resonant boost circuit with the Boost circuit. Compared to other traditional DC-DC converters, the improved topology of the power switches in this design exhibits lower voltage stress, lower diode current stress, fewer total components, and a common ground. The working mode and steady-state analysis of the converter are provided, and the stress derivation of the components and theoretical efficiency analysis are conducted. A comparison with other DC-DC converters is also performed. Finally, experiments are conducted on a 200W DC-DC converter prototype to verify the reliability of this converter.

Addressing the sensitivity of permanent magnet synchronous motors to external disturbances, a novel sliding mode control (NSMC) strategy is proposed to suppress sliding mode jitter and enhance speed regulation performance. First, an advanced non-singular fast terminal sliding mode (ANFTSM) surface and a new adaptive power rate reaching law (NAPRRL) were developed. A new switching function replaces the conventional sign function to enhance the system’s disturbance immunity and dynamic response speed. Then, the system’s anti-interference performance was further enhanced by introducing an improved novel sliding mode observer (INSMO) for feedback compensation of the aggregate disturbance. Finally, MATLAB/Simulink simulations and experimental validations demonstrate that the NSMC control strategy exhibits superior performance in both the start-up response and load disturbance phases, with enhanced dither-resistance, rapid dynamic response, and disturbance suppression capabilities.

This Manuscript delves into a deeper understanding of the fundamental concept of electrolysis, detailing the main types of Electrolyzers and conducting a meticulous analysis of their advantages and disadvantages. Additionally, this work presents a thorough examination of DC-DC and AC-DC converters, which are crucial in applications aimed at the production of green hydrogen, illustrating their functionality and applicability in great detail. Furthermore, the manuscript explores the diversity of power electronic systems employed in the production of green hydrogen, emphasizing the critical role of converters in this context. The investigation extends to effective strategies for integrating these technologies, aiming to optimize the green hydrogen production process. This study intends to be a significant contribution to the advancement of knowledge in sustainable technologies, highlighting power electronics as a fundamental vector in electrolysis, promoting the generation of renewable energies, and reinforcing the commitment to a greener and more sustainable future.

This work describes a novel wide tuning range ring voltage controlled oscillator (RVCO) for generating six-phase signals. The proposed circuit is realized by coupling two identical three-stage single-ended inverter based RVCOs. The coupling network injects the common mode signals from one RVCO to the other one and vice versa in cross-connected manner. Three-stage RVCOs used for coupling have been configured by modifying the conventional current-starved RVCO. The proposed six-phase RVCO is optimized using an improved version of Non-dominated Sorting Genetic Algorithm III (NSGAIII). In this algorithm, sigma scaling method is used to control the selection pressure and enhance the performance of the algorithm. The proposed RVCO oscillates at 4.3 GHz. The proposed oscillator can operate from 1.65 GHz to 4.62 GHz under the supply voltage of 1.5 V. This oscillator demonstrates a wide frequency tuning range of 95 %. The proposed RVCO has been designed in 0.18 µm standard CMOS technology and the chip area is 28 × 38.5 µm 2.

In low-voltage applications using low-Q LC filters, alias-free capacitor voltage acquisition can be achieved, but synchronous capacitor voltage sampling under high-Q filters used in high-voltage applications in grid-forming converters causes some degree of distortion and results in degradation of the power supply quality. And the 1.5 beat delay inherent in this approach limits the control bandwidth, reduces the stability region, and results in an inadequate time domain response. Despite these shortcomings, this approach is widely accepted in practice. This paper concludes that sampling 2us before the synchronous instant results in almost the same distortion as synchronous sampling, however, it can improve the dynamic performance of the system. A distortion-acceptable univariate feedback voltage dual-loop active damping control topology with much reduced computational delay is proposed, which is based on an internal active damping loop using a discrete lead compensator and a proportional resonance controller in the external voltage loop.

This paper studies the influence of the gate voltage of the power amplifier (PA) on the drain current and efficiency. This study proposes a theory of controlling input non-linearity to improve the efficiency of PAs. The theoretical efficiency of the inverse Class F PA which controlling input non-linearity is from 77 to 97%. A new design method for the inverse Class F PA that reconstructs the design of the load admittance space into a region instead of a point. To verify the validity of the proposed theory, a inverse Class F PA is designed and fabricated using a commercial 10W GaN high electron mobility transistor (HEMT). Results of the measurement show a high drain efficiency (DE) of 78.5%, a output power of 41.6 dBm and a large signal gain of 12.1 dB at 1.5 GHz. The overall PA’s size is controlled at 80*50 m m 2 .

With the renewable energy continuously access to the microgrid, the microgrid itself does not have the disadvantages of the inertia of the synchronous generator in the traditional grid is increasingly apparent, for which the generalized droop control (GDC) strategy is proposed. In the normal operation of the system, GDC has the advantages of large inertia and small active power overshoot, but when subjected to external frequency perturbations, the grid-supporting inverter with large virtual inertia is prone to large transient active power overshoot and oscillation. To address this problem, the article establishes small-signal models under different perturbations based on the GDC compared with the virtual synchronous generator (VSG) and further proposes two adaptive inertia control strategies: GDC adaptive inertia (GDCAI) and adaptive inertia for operation mode switching (AIOMS). By adjusting the virtual inertia appropriately, the rate of change of frequency (RoCoF) is maintained in the set range while improving the transient performance of the system, the methods of reduce-order of the system model and control parameter design is given, to reduce the frequency fluctuation while greatly reducing the active power overshoot and improving the response speed of the system. The effectiveness of the two control strategies is verified by MATLAB/Simulink simulation and StarSim hardware-in-the-loop (HIL) experiment.

The work elucidated in this scientific article presents a novel non-isolated high gain switched capacitor (HGSC) DC-DC converter engulfed for carbon neutral energy applications. A hybrid utilization of complementary switching approach switches enables simplified control and high voltage gain of HGSC even at low duty cycle owing to the switched capacitor along with boost inductors. Further, the proposed structure also features high efficacy, reduced voltage stress and current stress on semiconductor switching devices. The proposed HGSC DC-DC converter principle of operation along with the steady-state analysis and different switching stages were discussed in detail. Small signal analysis has been performed to analyze the stability of the proposed converter, whereas an averaging technique is performed to know its dynamics performance. Furthermore, the converter is thoroughly analyzed in terms of power losses. For comparing the practical efficiency of the designed converter, non-idealities voltage gain is derived. The efficiency of the proposed converter is validated practically and extensive performance comparison is carried out with other solutions in the literature. When a supply of input voltage 20 V feed into the proposed converter. It produces an output voltage of 140 V to 240 V output. A 200W laboratory proto model is developed; accordingly conducted extensive experimental analysis to validate the feasibility of the proposed HGSC DC-DC converter topology.

Inductive wireless power transfer (IPT) and capacitive wireless power transfer (CPT) are currently the two main wireless power transfer technologies. Combining the coils of the IPT with the plates of the CPT creates a hybrid wireless power transfer (HPT) system, which can improve the transmission performance but introduces higher parameter sensitivity. Therefore, achieving stable output power and constant transfer efficiency over a wide range of coupling coefficient variations is still a major challenge for HPT. In this work, the parity-time (PT) symmetry theory is applied to an SS-type HPT system, and a circuit model of the PT-based HPT system is developed by using coupling capacitance and coupling inductance. The effect of connecting the plates to the homonymous end or heteronymous end of the coupling coils on the PT-symmetry range of the HPT system is discussed. It is found that the heteronymous end connection of the coils can effectively increase the range of constant output power and stable transfer efficiency. Finally, a prototype is built to verify the feasibility and effectiveness of the proposed PT-based HPT system. The transfer efficiency remains constant in the PT-symmetric range, and the inductive and capacitive coupling coefficients are smaller compared to IPT and CPT systems with the same parameters.

As the increasing demands for the constant voltage (CV) charging of multiple loads, this article proposes an LC compensated wireless power transfer (WPT) system with multiple CV outputs function. The proposed WPT system can achieve multiple voltage outputs without decoupling method. Each voltage output channel is composed of a compensation capacitor and a compensation inductor connected in series. By configuring different compensation inductors and capacitors for each output channel, it can achieve different CV outputs without affecting the output voltage of other output channels. In addition, the system can achieve near-zero phase angle (ZPA) and zero-voltage switching (ZVS) operations, which can improve system efficiency. Finally, the correctness and rationality of the proposed WPT system is verified by built an experimental prototype with two CV output channels.

This paper proposes a readout scheme that utilizes a pair of differential-clocks-assisted time-to-digital converter (DCA-TDC) in CMOS image sensors (CISs). The DCA-TDC utilizes only half the number of ordinary TDC delay chain units by employing a binary-weighted search algorithm to determine the most significant bit (MSB) for fine quantization of a single-slope analog-to-digital converter (SSADC). The layout area and dynamic power introduced by the improved DCA-TDC delay chain are reduced by half compared to an ordinary TDC delay chain. The proposed SS ADC is designed and simulated using the 0.11 µm standard CMOS process. In the design environment with an analog voltage of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and a temporal resolution of 500 ps, this design is an 11-bit ADC with column-level power consumption of 65.4 µW, a row conversion time of 2.72 µs. Furthermore, it achieves an effective number of bits (ENOB) of 10.75 and a figure-of-merit (FoM) of 103.3 fJ/step. By interpolating a DCA-TDC, the quantization speed is faster than a traditional SS ADC. This scheme offers an effective solution for implementing high-frame-rate CISs.

Accurate estimation of lithium-ion battery state of energy (SOE) is an important prerequisite for prolonging battery life and ensuring battery safety. To achieve a high-precision estimation of SOE, this study focuses on ternary lithium-ion batteries and proposes an SOE estimation method that combines limited-memory recursive least squares (LM-RLS) with strong tracking adaptive window Multi-innovation cubature Kalman filtering (STF-MCKF). A finite set of data is used for model parameter updates at the current time to solve the problem of data saturation and improve the identification accuracy of the RLS algorithm. By utilizing the STF algorithm, the CKF algorithm is optimized to enhance its robustness under strong disturbances. An adaptive window Multi-innovation strategy is proposed to improve the accuracy of SOE estimation and the stability of the CKF algorithm while maintaining a balance between computational complexity and estimation accuracy. To validate the effectiveness of the algorithm, experiments are conducted under DST and BBDST conditions. The results show that the STF-MCKF algorithm has a maximum convergence time of 4s and an SOE estimation error within 1.04% under DST conditions. Under BBDST conditions, the STF-MCKF algorithm has a maximum convergence time of 3s and an SOE estimation error within 2.34%. Furthermore, the STF-MCKF algorithm demonstrates good stability under both the two conditions, indicating the effectiveness of the proposed improved algorithm for lithium battery SOE estimation.

The demand for wireless power transfer (WPT) systems that can maintain a constant voltage output (CVO)characteristic is gradually increasing in some practical application areas of WPT, such as industrial power supplies. However, existing CVO-type systems are often limited by the parameter design of the loosely coupled transformer (LCT) and the configuration of the receiver side is not compact enough. Therefore, this paper proposes a strongly coupled system with CVO function composed of capacitor-inductor-capacitor-none (CLC-N) topology. The system’s primary side uses a CLC compensation, while the secondary side conforms to a minimalist design without the need for compensation components such as capacitors and inductors. The initial segment of the paper pertains to the discussion of the conditions required to satisfy both zero-phase-angle (ZPA) and CVO functionality of the suggested system. Subsequently, an in-depth approach to parameter design is outlined, accentuating that the output voltage remains unrestricted by the LCT’s parameters. Additionally, this paper examines the realization of zero-voltage switching (ZVS) within the suggested system, as well as the influence that variations in compensation components have on the CVO function. To underscore the benefits of the suggested CVO-type WPT system that employs CLC-N compensation, the paper presents a comparison with a range of other CVO-type WPT systems. Ultimately, an experimental prototype is fabricated to test the theoretical framework, and the results from these experiments confirm the feasibility of the suggested CVO-type WPT system based on CLC-N compensation.