Passive linear voltage dividers are an essential part of the voltage sensing and detecting circuits. In this paper, a novel voltage divider is designed in 180nm CMOS technology and is validated with LTSpice simulations. The proposed circuit features very low steady current consumption and as a result, very little power dissipation around 200-300pW.

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

Power management in integrated circuits is critical and some ICs require voltages to be applied in a particular sequence. Integrated circuits consist of various distinct sub-circuits and power delivery to each of those circuits at the proper time is required for proper operation. Some examples are Subscriber line interface circuit (SLIC), switching voltage regulators, etc. Thus, startup delay circuits are necessary as they ensure the delivery of power to circuits at the appropriate time. Time delays are conventionally generated by resistor-capacitor pair but the time constant is very small, for higher time delay, we have to increase resistor-capacitor sizes which require more space and is not economical. In this paper, a new technique is proposed for the generation of sufficient time delays eliminating the need for larger resistor and capacitor combination. The proposed startup delay circuit is designed in 180 nm. CMOS process and simulated in LTSpice.