This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 µm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (IQ) of 7.76 µA and 5.4 µA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

This brief presents a novel level-shifter circuit for high-frequency high-voltage (HV) gate-drives. The proposed level shifter (LS) is designed based on a capacitive-coupler/current mirror/ latch structure which helps to extend operation voltage of a floating supply into the negative range, achieves sub-ns and constant delay, and consumes very low power from the floating supply. Additionally, common-mode noise cancellers based on a cross-current mirror and transmission gates are also presented to enhance the dV/dt immunity of the LS against slewing of the floating ground. Implemented in 0.18 µm HV BCD-on-SOI (bipolar-CMOS-DMOS on silicon-on-isolator) process, the post-layout simulation of the proposed design shows a delay of 680 ps, 200 V/ns of dVSSF/dt slew rate immunity, It dissipates no static power and only 8.1 pJ/transition from the floating supply, improving FoM1 and FoM2 of the proposed LS by 3 times and 11.7 times compared to respective state-of-the-art works.

This paper presents a new dual-inductor hybrid boost converter (DI-HBOC) with two inductors located at the output. This structure allows continuous current delivered to the load, thus, reducing the output filtering capacitor size and the output voltage ripple. By relocating the inductor at the output, which is the lower current path, the conduction loss on the inductor can be significantly reduced. The right half plane zero (RHPZ) in the control-to-output transfer function can also be eliminated; therefore, a simple pulse-width modulation (PWM) voltage-mode controller can be used for the proposed DI-HBOC while still achieving high closed-loop bandwidth and fast transient response. The distinct features of the proposed converter are analytically demonstrated. A 12-to 24 V DI-HBOC and a conventional BOC (CBOC) using low-RON GaN switches with PWM voltage-mode controller are also implemented in PSIM for verification and comparison. The simulated peak power efficiency is 97.4 % that is 1.17 % higher than the CBOC. At 3 A load current, the power efficiency is improved by 9.7 % and the output ripple is only 17.5 mV, 6x lower than in CBOC.