Digital Delta Sigma modulators (DDSM) are used in applications that require a reduction of the wordlength of a digital signal. In the presence of non-idealities, the quantization error of the DDSM can interact with nonlinearities further along the signal chain and generate spurious tones in addition to excess noise.

Digital Delta Sigma modulators (DDSM) are typically used in phase locked loops for fractional frequency synthesis. Different types and configurations of DDSMs have been presented in the past which have distinctive characteristics in terms of spectral shaping of the quantization errors, spur immunity and implementation cost. In this paper we present a family of DDSMs that have high spur immunity and low folded noise when used in fractional-N frequency synthesizers.

The interaction between quantization noise intro-duced by the divider controller and memoryless nonlinearities in a fractional-N PLL causes fractional spurs to occur. This paper presents a comprehensive theory to explain why combinations of quantizers and memoryless nonlinearities produce fractional spurs. Necessary and sufficient conditions for spur-free behavior in the presence of an arbitrary memoryless nonlinearity or linear combinations of sets of arbitrary memoryless nonlinearities are derived. Finally, an upper limit on the number of nonlinearities for which a quantizer can exhibit spur-free performance is derived.