This brief introduces an optimized architecture for serial commutator (SC) pipelined fast Fourier transform (FFT) with fully-real data paths, utilizing a novel data management scheme based on bit-dimension permutation circuits. By employing this approach, we minimized multiplexer utilization by 80% in every processing element (PE) and 50% in every permutation circuit of each stage compared to the conventional SC architecture. Additionally, the proposed structure achieved full hardware utilization with a natural order input/output (I/O) datastream. Experimental results demonstrate that our architecture reduced look-up table (LUT) logic by 31% compared to the prior design.

In this brief, we present a novel pipelined architecture for real-valued fast Fourier transform (RFFT), which is dedicated to processing serial input data. An optimized algorithm is proposed for stage division in RFFT to achieve an area-efficient RFFT computing structure with full hardware utilization. A single path butterfly and a real rotator are merged into one processing element (PE) in each stage, except the last stage, to reduce hardware resource utilization. In addition, a novel shift-adder is designed for N-point RFFT with W-bit signals, and a new data management method based on the PEs is proposed, which saves resources with a more regular flow graph.