Phase-locked loop (PLL) impacts the small-signal and transient stability of grid following (GFL) inverters in power networks. Extensive analysis of their impact on system stability subject to faults has been presented in literature while the impacts of malicious attacks on PLL have not been well understood. This letter reveals the interaction between grid forming and GFL inverters in a microgrid when PLL has been maliciously attacked. The analysis reveals the risk of system blackout due to voltage collapse triggered by inverter current limitation. Reduced mathematical model has been derived and extensive analysis undertaken to demonstrate the phenomenon.

The transition towards cleaner energy resources has led to the increased penetration of converter-interfaced distributed generators (DGs) and the extensive use of information & communication technologies (ICT) in power systems. Although recent efforts have been made to understand, model, and classify converter interactions, much remains unexplored. This complex dynamic structure of emerging smart grids, is a result of DGs' advanced controllers, communication links and the hardware itself. In that framework, the digitization of power systems introduces new vulnerable points that are susceptible to cyber threats. Building on the knowledge stemming from computer science, cyber attacks targeting power systems have been classified, with false data injection (FDI) attacks identified as one of the most common threats. In this paper, the impact of a microgrid's operational and design parameters on its cyber resiliency under FDI attacks on the secondary controller is showcased. In particular, in a modern islanded microgrid comprising grid forming inverters for increased flexibility, and distributed secondary control being implemented as part of its hierarchical control, the impact of the droop gain and the R/X ratio of the lines on the microgrid's inherent cyber-resilience against FDI attacks is demonstrated. In the analysis the current limitation is taken into consideration as studies often focus solely on the small signal stability properties of a system, overlooking the power constraints.

Aiming to investigate the possible interactions between smart grid components during transient events, an advanced hardware-in-the-loop testing chain for the validation of novel smart grid solutions is proposed in this paper. The testing chain is directed towards both academic and industrial HIL users, e.g., relay manufacturers, power electronics manufacturers and DSOs/TSOs. All different hardware-in-the-loop simulation setups, ranging from simple local simulations up to more elaborate, geographically distributed hardware-in-the-loop simulations, are discussed, forming a solid testing chain. The interactions during transients, which can be investigated at each step, are analytically derived to emphasize the insights that each step can offer to the performed component validation. To highlight the applicability of the proposed hardware-in-the-loop testing chain, when validating smart grid components, a case study concerning the testing of a microgrid transition algorithm, between the interconnected and islanded modes of operation, is considered for a real microgrid. Particularly, the interactions between an advanced grid-forming inverter and the already existing grid-following inverters of the microgrid are investigated during normal and abnormal grid conditions, while following the appropriate steps of the proposed testing chain.

A novel power hardware-in-the-loop interface algorithm, the Virtual Shifting Impedance, is developed, validated and demonstrated in this paper. Building on existing interface algorithms, this method involves shifting a part of the software impedance to the hardware side to improve the stability and accuracy of PHIL setups. However, compared to existing approaches, this impedance shifting is realized by modifying the command signals of the power amplifier controller, thus avoiding the requirement for hardware passive components. The mathematical derivation of the Virtual Shifting Impedance interface algorithm is realized step-by-step, while its stability and accuracy properties are thoroughly examined. Finally, the applicability of the proposed method is verified through PHIL simulation results.