In this work we fabricate and electrically demonstrate a 65nm technology- compatible PCM pillar device using Sc- doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on 300mm wafer in 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching.  Detailed knobs how to improve stack in terms of CD, thickness (of electrode and chalcogenide material) and Sc doping are presented. The optimized stack shows AC switching from 300ns-1µs for SET and RESET with current in the order of  mA and programming voltage less than 2.5V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1hour retention at 85℃ is achieved for the optimized stack of C:Si /50nm ST:Sc 6%. The fabricated devices show potential to extend PCM technology towards high-speed SCM applications.