This work studies the 3D stacking of an approach to silicon carbide (SiC) integrated circuit (IC) chips using flip-chip technology with gold stud bumps for high-temperature (up to 600°C) applications. Standard photolithography, sputtering deposition, and lift-off process were used for chip metallization and patterning with titanium (Ti), tantalum silicide (TaSi2), platinum (Pt), and gold (Au) thin films. Gold stud bumps were used to bond the SiC chips with a flip-chip die bonder forming a daisy chain connection. Die shear tests were conducted, and the electric resistance of the daisy chain interconnect between the chips was measured before and after thermal aging in the air at 600°C for up to twelve days. It is found that the electric resistance of the daisy chain interconnects decreases with heating and stabilizes at about 1 Ohm for 36 bumps, showing that the thermal aging process improves the electric performance of the interconnect with gold stud bumps. The destructive die shear test shows that, with thermal aging, the shear force decreases for the chip stacks and stabilizes at about 15-gram force (gf) per bump with TaSi2 diffusion barrier in the metallization. In contrast, the shear strength increases for the chip stacks without TaSi2 barrier in the metallization.

Silicon carbide integrated circuits have been demonstrated to operate at high temperatures, such as ~460ºC at the Venus’ surface, for two months and for over a year at 500ºC. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300ºC. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, 3D packaging is a notable advantage. In this work, 3D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold contact pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3D SiC chip packages are subject to a 600ºC thermal aging process in air for up to ten days. This 3D SiC chip packaging has promise for long-duration high temperatures (up to 600ºC) applications and may be potentially of use for applications such as Venus’s surface sensing and telemetry.

This paper compares different types of GAA FET structures at 3 nm technology node using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. Single gate and gate stack structures are included in the analysis. The performance is evaluated using the key device parameters such as on-state current, leakage-current, thresh-old voltage for transfer characteristics, drain-induced barrier lowering (DIBL) and subthreshold slope (SS) for short-channel effects. Among the four GAA structures we found that, under the same effective width, Lateral Nanowire structure shows the highest on-state current, but also the worst performance in short channel effects. In contrast, Vertical Nanosheet shows the lowest DIBL and SS, thanks to