This study introduces the first-of-its-kind Reconfigurable Threshold Logic Gate (R-TLG) using Ferroelectric FET (FeFET) devices. The experimental measurements of 28 nm FeFETs demonstrate that four distinct threshold voltage (V TH) states can be reliably programmed in presence of variation. We employ such multilevel FeFETs to implement a novel R-TLG in which the weights of the threshold functions are encoded within the four different analog states of FeFETs. Our R-TLG consists of merely 26 transistors, which is less than the number of transistors in a single D-FF gate, yet it is capable to realize 13 different complex Boolean functions. The total number of transistors to realize those functions in convectional CMOS reaches 220, which is 8.5x higher than what our FeFET-based R-TLG requires. This translates into a remarkable area saving, which is very crucial in an era where computational demands incessantly escalate due to AI applications. Further, the variety of Boolean functions that our R-TLG realizes not only optimizes area, but also bolsters IP security through camouflaging because thieves must navigate a much larger design space while reverse engineering.

We have developed a comprehensive modeling framework to explain the switching characteristics of BEOL-compatible FeFET with an amorphous IGZO channel. Our TCAD-based modeling framework, calibrated against measurement data, jointly incorporates a) the distributed channel, b) a physics- based nucleation-limited switching dynamics model for multi- domain ferroelectric polarization (PFE) and c) the domain-domain interaction. To our knowledge, this is the first demonstration of a physics-based comprehensive model of BEOL-compatible FeFET. Our model reproduces and explains the experimentally- observed abrupt current jumps in the reverse and forward DC sweeps. Further, our model is capable of processing arbitrary input waveforms such as quasi-DC and different kinds of pulse trains used in neuromorphic applications. This comprehensive modeling framework would enable researchers to explore the BEOL FeFET applications and guide device optimization and development.

Today’s data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET. We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.