Bit-pattern detection is essential to network intrusion detection systems. In this paper we are attempting to offer a universal solution to the problem of bit pattern detection through the use of a throughput focused architecture. The circuit presented is an accelerator implemented on an FPGA. By exploiting the technique of pipelining, we achieve throughput in the magnitude of Terabits while minimizing hardware consumption. Two versions of the circuit are presented. The first version consumes very little in terms of hardware but has limited throughput and detection capabilities. The second version uses the first as a building block to increase the size of inputs per clock cycle. It consumes more resources; however, it is the version which can provide the highest throughput.
