Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on September 2023. Abstract: Power hardware-in-the-loop (PHIL) is a modern experimental technique that allows emulation of a full-scale converter (FSC) with the combination of a scaled-down converter (SDC), power amplifier, and real-time simulator, thus enabling the study of real-time interactions of power electronics with large power systems. However, assembling an accurate scaled-down replica of an FSC with off-the-shelf laboratory SDCs is practically impossible due to a mismatch in per unit losses, as well as in the impedance of the L/LC/LCL filter. Consequently, the scaled-up power flow capability of SDCs differs from FSCs, restricting emulation to smaller regions of the four quadrants than those corresponding to the FSCs nominal active and reactive capacity. These PHIL test beds cannot be used to emulate FSCs demanding bidirectional active and reactive power flow. Any scaling method on SDCs, emulating the entire operation of FSCs, demands underutilisation of SDCs, reducing the advantages of PHIL tests. This paper, therefore, proposes a physics-informed scaling method that exploits power capability curves to emulate FSCs in all four quadrants of operation. This method is independent of SDC topology, filter type, and interfacing methods. A visual identification of the semiconductor device constraints bounding the emulation is also presented, utilizing the physics of converter control. A theoretical analysis of the proposed method is presented, followed by validation with MATLAB simulations and experimental tests using a 50 kVA SDC.

Manuscript submitted to the IEEE Industry Applications Society’s Open Journal of Industry Applications on January 2023. Abstract: Power hardware-in-the-loop (PHIL) is an experimental technique that uses power amplifiers and real-time simulators for studying the dynamics of power electronic converters and electrical grids. PHIL tests provide the means for functional validation of advanced control algorithms without the burden of building high-power prototypes during early technology readiness levels. However, replicating the behavior of high-power systems with laboratory scaled-down converters (SDCs) can be complex. Inaccurate scaling of the SDCs coupled with an exclusive focus on instantaneous voltages and currents at the fundamental frequency can lead to PHIL results that are only partially relatable to the high-power systems under study. Test beds that fail to represent switching frequency harmonics cannot be used for studying harmonic penetration or loss characterization of large-scale converters. To tackle this issue, this paper proposes a harmonic-invariant scaling method (HISM) that exploits the VA rating of preexisting laboratory SDCs for more accurately replicating harmonic phenomena in a PHIL test bench. Firstly, a theoretical analysis of the proposed method is presented and, subsequently, the method is validated with MATLAB simulations and experimental tests.