Employing high switching speed wide bandgap (WBG) devices improves the efficiency of industrial drive inverters, but can result in motor overvoltages for shorter lengths of cable between the inverter and motor. These overvoltages are caused by high frequency impedance mismatches resulting in reflection of the voltage pulse edges of the inverter output. Forwards and backwards travelling reflections interfere and in the worst case cause double the DC-link voltage to appear across the motor terminals. In this paper this doubling of the motor voltage stress is observed with only a 10 metre cable. To mitigate the motor overvoltage a novel method using a differential mode coupled inductor between the paralleled half bridges and the phase output is proposed. By adding a delay time between the half bridges at every switching event a quasi-three-level output is produced which can actively cancel reflected voltage waves, eliminating the cause of motor overvoltages. The method can be utilised for three phase inverters, and when using paralleled devices only requires one additional inductor per phase. A design process for the coupled inductors is given which aims to minimise the circulating current between the half bridges and therefore give minimal increase in conduction losses due to imbalanced current sharing. These additional conduction losses and other limitations of the proposed method are analysed. An inverter utilising this proposed method is implemented and compared to a filter designed for overvoltage mitigation. The novel method achieves near perfect overvoltage mitigation with much smaller additional volume and much lower losses than the filter. Furthermore the losses when using the active mitigation method are very similar to using the inverter with no overvoltage mitigation.

Class II multi-layer ceramic capacitors (MLCCs) employing ferroelectric materials have been widely utilized as the primary energy storage and transfer element in high-frequency resonant converters due to their ultra-high energy density. In these applications, MLCCs experience large-signal and high-frequency electrical excitations superimposed on biased voltages, burdening converters’ efficiency due to their significant power loss. However, little has been published to reveal the large-signal loss characteristics of Class II MLCCs under such realistic operating conditions. This paper develops a novel characterization method to experimentally extract MLCC power loss using a resonant-Sawyer-Tower (Res-ST) circuit under large-signal and wide-frequency-range excitation with DC bias voltage. A general loss modeling approach based on Steinmetz’s Pre-electricized Graph (SPeG) is also proposed to accurately correlate the large excitation amplitude, wide-range frequency, and DC bias voltage. In this paper, the SpeG model first provides the material-specific volume loss density of four common dielectric materials and then can be easily extrapolated to evaluate the loss of the MLCCs with different rated voltage$\&$capacitance but employing the same dielectric material. In order to extend the material-specific SPeG model to device-level application, this paper also prepares an easy-to-follow tool, dielectric thickness observer (DTO), to estimate the dielectric microstructural geometry by tracking the $C$-$V$ characteristics provided in the product datasheet. The combination of the proposed loss characterization method, SPeG model, and DTO can be used as a very convenient and accurate tool to estimate the power loss of MLCCs in different applications, in particular high-frequency resonant tanks. This article is accompanied by SEM images and MATLAB code demonstrating the effectiveness of the proposed DTO.