A 2.72 µ s row conversion time 11-bit column parallel single slope ADC
with differential-clocks-assisted TDC interpolation for CMOS image
sensor
Abstract
This paper proposes a readout scheme that utilizes a pair of
differential-clocks-assisted time-to-digital converter (DCA-TDC) in CMOS
image sensors (CISs). The DCA-TDC utilizes only half the number of
ordinary TDC delay chain units by employing a binary-weighted search
algorithm to determine the most significant bit (MSB) for fine
quantization of a single-slope analog-to-digital converter (SSADC). The
layout area and dynamic power introduced by the improved DCA-TDC delay
chain are reduced by half compared to an ordinary TDC delay chain. The
proposed SS ADC is designed and simulated using the 0.11 µm
standard CMOS process. In the design environment with an analog voltage
of 3.3 V, a digital voltage of 1.5 V, a clock frequency of 62.5 MHz, and
a temporal resolution of 500 ps, this design is an 11-bit ADC with
column-level power consumption of 65.4 µW, a row conversion time
of 2.72 µs. Furthermore, it achieves an effective number of bits
(ENOB) of 10.75 and a figure-of-merit (FoM) of 103.3 fJ/step. By
interpolating a DCA-TDC, the quantization speed is faster than a
traditional SS ADC. This scheme offers an effective solution for
implementing high-frame-rate CISs.