In the context of paralleled Silicon Carbide (SiC) dies at low stray inductance, the current imbalance proves to be exceptionally sensitive to the static parameters of the devices. Even under conditions of full layout symmetry, significant current mismatch persists. This issue becomes prominent in emerging technologies utilizing standard cell design and die embedding, characterized by low stray power loop inductance. Traditional packages with relatively high stray inductance do not exhibit this particular problem. Addressing the challenges posed by these low-inductance technologies, this paper introduces a passive current-sharing method employing AC-coupled inductor. The proposed method is demonstrated through the implementation of a highly integrated converter with power loop inductance less than 1 nH. Notably, the presented approach is straightforward to implement and achieves near-perfect current sharing among paralleled dies, thereby facilitating the realization of high-current rating converters.