An improved approach to the AND-OR-Multiplexer SET filter technique is presented as a solution for mitigating both single and multiple-bit upsets. Through simulations and experimental validation, this novel method addresses single-event upsets (SEUs) and multiple-bit upsets (MBUs) in digital circuits. The technique integrates AND-OR gate circuits in parallel with a two-input multiplexer, resulting in a unified circuit capable of mitigating both single and multiple-bit upsets, regardless of whether the input state is high or low. This paper details the results from simulations and experimental investigations, where the new method is applied to various sequential circuit configurations in a commercial Flash-based FPGA, specifically the 0.13μm ProASIC3E product family (A3PE), subjected to proton beam irradiation. The implementation and evaluation conducted in-beam demonstrate the technique's effectiveness in eliminating SEUs and MBUs compared to designs without mitigation. Proton testing indicates that this method significantly reduces single and multiple-bit upsets compared to traditional Triple Modular Redundancy (TMR) and unmitigated designs.