This paper presents a novel methodology for design space exploration and resource optimisation of three-dimensional Networks-on-Chip (3D NoC) architectures using hypergraph modelling and genetic algorithms. The proposed approach combines the mathematical rigour of hypergraph theory with the evolutionary search capabilities of genetic algorithms to efficiently explore the vast design space of 3D NoC configurations. Unlike existing vendor-specific tools, our framework provides a vendor-independent solution for NoC architects and designers. The key contribution is the development of Performance-Cost-Ratio (PCR) functions that enable quantitative evaluation of different topologies and routing algorithms. We validate our framework through two compute-intensive use cases: double SHA256 cryptographic operations and real-time facial recognition. Experimental results demonstrate significant improvements in both applications, with the optimised architectures achieving up to 33% reduction in latency, 40% increase in throughput, and 30% reduction in power consumption compared to baseline implementations. The insights and techniques presented have farreaching implications for developing efficient and scalable NoC solutions as processor designs advance towards kilo-core scales and beyond.