This paper presents a modified design for a Carry Save Multiplier (CSM) that aims to reduce power consumption compared to conventional approaches. The key modifications include replacing the conventional full adder (FA) with three different adder designs-Improved Full Adder (IFA), Hybrid-Pass logic with Static CMOS (HPSC), and Transmission Gate Adder (TGA)-and replacing the conventional vector-merging adder (CVMA) with a delay and energy-efficient Modified Square Root Carry Select Adder (MSCA) for the final addition step. The power consumption is reduced by approximately 84.66% when using the Transmission Gate Adder (TGA) instead of the Improved Full Adder (IFA), and by approximately 78.22% when using the Hybrid-Pass logic with Static CMOS (HPSC) adder instead of Improved Full Adder (IFA). The Transmission Gate Adder (TGA) when used in the multiplier circuit achieved the lowest power consumption with a reduction of approximately 72.04% compared to the IFA's power consumption. The Hybrid-Pass Logic with Static CMOS (HPSC) adder when used in the multiplier circuit has a reduction of 50.81% in comparison to the IFA. The modified CSM architecture, demonstrates significant power savings compared to traditional designs while maintaining multiplication performance, making it an attractive choice for high-speed, low-power digital systems.