Static random access memory (SRAM) plays a vital role in the overall power consumption of system-on-chip (SoC), particularly in the portable applications. Supply voltage overscaling is one of the most commonly used design methods to reduce the power consumption of SRAM, which degrades the speed and stability. This paper proposes a high-speed/stability 10T SRAM (HS10T) cell with high read stability and write ability for low-voltage operation. A discharge transistor and the power-gating structure are used in SRAM to improve the write ability and reduce write delay with relatively low supply voltage. Meanwhile, the read-decoupling structure can improve the read static noise margin (RSNM) by separating the reading circuit from the writing circuit. The simulation results show that the delay and power-delay-product (PDP) of the proposed SRAM cell are reduced by 86.22% and 82.56% respectively compared to the latest similar work. Additionally, the average write margin (WM) of the HS10T SRAM cell has also been improved by 4.14% while ensuring high energy efficiency.