This work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects. A rigorously calibrated TCAD model, validated against experimental CFET data, is employed to quantify the impact of metal gate granularity (MGG)-induced work function variation (WFV) and random dopant fluctuation (RDF) on key device parameters, including the threshold voltage (V TH), on-state current (I ON), and off-state current (I OFF). Temperature-dependent variability is systematically analyzed to further elucidate the behavior of these advanced devices. To capture the dynamic effects of aging, the reaction-diffusion (RD) framework-which accounts for defect generation due to Negative Bias Temperature Instability (NBTI)-is implemented in TCAD, enabling detailed modeling of trap generation and the corresponding V TH shifts in p-type transistors under varying gate stress biases (V GSTR) and operating temperatures. At the circuit level, a full array of 6T-SRAM cells with the requisite peripheral circuits is simulated using SPICE after careful calibration of the the industry-standard compact model of gate-all-around (BSIM-CMG) against the TCAD data. Variability analysis reveals that the access disturb margin achieves a cell sigma (µ/σ) of 17.4 at nominal supply voltage, significantly exceeding the 6σ robustness criterion for read disturbances. Moreover, as the operating temperature increases from 300 K to 398 K, the read static noise margin (RSNM) and hold static noise margin (HSNM) degrade by 13.7% and 6.37%, respectively, while the write static noise margin (WSNM) improves by 18.3 %. These findings provide critical insights into the design trade-offs and reliability challenges of CFET-based SRAMs.