Power cycling reliability is one of the most rigorous methods to evaluate the durability of power semiconductor devices against real-life varied electrical and thermal stresses. The corresponding test results can generate lifetime models to predict the service life in operating conditions. This paper provides an overview of the power cycling reliability testing for power semiconductor devices, focusing on both legacy Si and new wide bandgap (WBG) devices. It begins by presenting the power semiconductor packaging trends, their evolving failure mechanisms, and the power cycling test methods. Different testing standards, lifetime models, and their challenges are then discussed. Special attention is given to WBG devices, examining various testing methods and their impacts. A generic lifetime model for different semiconductor materials and packaging technologies is provided based on above 200 samples collected from the existing literature, which can serve as a useful tool for reliability evaluation. Finally, the limitations and associated open questions are discussed to identify future research opportunities.

This paper proposes an active learning framework to address a longstanding research question: how much data is needed for data-driven power electronics designs. The proposed method can automatically explore the optimal scenario using minimal data while achieving the desired accuracy. To demonstrate the proposed method, the reliability-oriented design (ROD) for a traction converter is used as a case study. While traditional methods achieving ROD necessitate extensive simulation and experiments, the proposed method uses surrogate models and active learning to achieve the desired accuracy with the minimal computational requirements. The performance of the proposed method has been verified by experimental measurements. The computation cost is reduced by 62.5% compared to the traditional ROD method.

In this paper we propose a new evaluation method for revealing the inner structure information from the measurements of the thermal transient response of semiconductor devices. In contrast with the conventional methods based on the frequency domain deconvolution, the proposed method casts the problem as a regularized least squares problem for an integral equation directly in the time domain. The regularization is selected based on the knowledge of certain physical quantities involved in the measurement. We observe that the thermal time constant spectrum produced by the proposed method tends to have a better capability of identifying two adjacent parameters. With the benchmark of the true values of the thermal networks, the structure function of the proposed method reduces the relative error by an order of magnitude. A series of simulations based on different parameters and structures verify the viability and performance of the proposed method. A proof-of-concept experiment based on a commercial power semiconductor device also validates the effectiveness of the proposed method.