This work develops a low-power and low-voltage differential Gm-C filter structure that effectively achieves selfcommon-mode control (SCC), including DC stabilization and common-mode (CM) rejection, without employing extra control circuitry. The structure relies upon an incorporation of voltageinverting amplifiers to make it inherently contain no CM positive feedback loops for DC stabilization, and to enable splitting of the core transconductors into pairs for CM signal rejection. A DC CM stability analysis reveals that stabilization of the SCC structure can be reached without any dedicated CM control circuitry. An analytical comparison on power consumption of a high-order lowpass Gm-C filter implemented using an inverter-based transconductor for the SCC structure and the same transconductor with a CM control network (the Nauta’s technique) for the conventional structure indicates theoretical overhead power saving by over 50%. Furthermore, an even higher overhead power saving at over 70Ên be achieved in the complex SCC Gm-C filter because no additional inverting amplifiers are required to eliminate CM positive feedback loops in the crossing transconductors for complexification. The impact of the inverting amplifiers on the noise and frequency characteristics as well as the compensation technique are outlined to enable design optimization. The SCC filter was verified via extensive simulations of a 5th-order 1.1-MHz elliptic complex filter in a 0.18-m CMOS process. As compared to the conventional filter counterpart with similar SNR (~63dB) and inband/out-of-band SFDRs (~52dB/56dB), the proposed structure yields an overhead power saving by 70% with an improved figure-of-merit over 40% under a 1-V supply.

A phase-locked BPSK/QPSK demodulator with a single-phase voltage-controlled oscillator (VCO) is proposed. Relying on a linear voltage/phase-difference characteristic of the phase detector, a phase-control process of this single-loop demodulator architecture is simple and truly modular. Such process is done by selective voltage shifting and re-scaling to ensure no significant change at the VCO’s input regardless of the incoming modulated signals’ phase. The prototype has been fabricated in a 0.18-μm CMOS process operating under a 1.8-V supply with a 60-MHz carrier. The BPSK and QPSK demodulators achieve maximum data rates of 25 Mbps while consuming 0.68mW and 0.79mW, respectively with the corresponding energy per bit figures of 27.2 and 31.7 pJ/bit.