Improving power delivery and management plays a key role in minimizing the cost of building and operating future green data centers to meet the fast growth of high-performance computing. Toward this important goal, this paper presents a new complete power delivery architecture to bridge AC grid voltages to core levels for computing loads using only 2 conversion stages with new converter topologies. The first stage converts a commercial AC line voltage of 90V-110V to a 48-60V intermediate bus with power factor correction (PFC). The second stage converts the bus voltage to core voltages of ~1 V with high current density and simple duty cycle control. Individually, the first stage was measured at 96.1% peak efficiency for output currents ranging in 0-4.5 A, while the second stage achieved 90.7% peak efficiency with a load range of 0-220 A at 1 V. Measured peak power densities are 73 W/in3 for the first stage and 2020 W/in3 for the second stage. In combination, the direct conversion from a line AC voltage of ~110 VAC to 1 VDC achieves a peak efficiency of 84.1% while providing output currents up to 160A.

This paper investigates the origin of the flying capacitor voltage imbalance in hybrid converters. By observation and logical deduction, an intuitive voltage-charge relationship is established which can give a general explanation of the flying capacitor voltage balance in hybrid converters. This relationship can establish a relatively simple and intuitive method to identify the difference of balance performance in hybrid converters for Vout<(Vin /N) cases. Converter with even number of inductor charging intervals, are shown to be susceptible to flying capacitor voltage imbalance, while flying capacitors in hybrid converters with inductors having odd charging intervals have inherently balanced operations. As a direct result of the analysis, a new symmetric operation of FCML converters is introduced to achieve an inherent balance of flying capacitor voltages. Hardware implementations and experiments have been carried out for verifications of the analytical analysis and the new symmetric operation.

Gate driver circuits to ensure proper turn-on and turn-off for power switches are essential parts of a power converter design. They become even more important for multilevel converters where multiple switches are operated at active voltage domains. Recent favorable use of Gallium-Nitride (GaN) devices for power switches makes gate driving even more challenging as the switch performance and reliability are more sensitive to variations of the gate driving signals and power compared with traditional power MOSFETs. This paper discusses gate driving methods using a multi-level multi-inductor hybrid (MIH) converter as the demonstration prototype to address two key challenges in designing gate drivers: 1) providing level-shifted PWM signals to active voltage domains and 2) powering schemes for gate driver circuits. To solve the first challenge, an optimal use of available half-bridge drivers is devised to eliminate the need for separate signal isolator chips. This method was implemented and verified in a MIH converter prototype for 48-V Point-of-Load (PoL) applications using three different powering schemes for gate drivers, including isolated power modules, regulated supplies from switch blocking voltages, and cascaded bootstrap power rails with regulations. The gate driver techniques and powering schemes are compared experimentally in terms of performance to illustrate their benefits and trade-offs.