This brief proposes a low power mixed-signal foreground calibration algorithm of a pipeline ADC, using a digitally controlled re-configurable switched capacitor multiplying DAC (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain towards its ideal value to achieve the ideal ADC output linearity. In this paper, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital backend unit response. The proposed technique has been verified in 0.18 um CMOS process using the cadence virtuoso tool by simulating an 11- bit pipeline ADC which contains a 1.5-bit nonideal pipeline stage followed by a 10-bit linear back-end ADC (BE-ADC). Simulation results demonstrate the recovery of the lost linearity of a 11 bit pipeline ADC post calibration.