IQ mixers and complex mixers are both used to cancel the image band signal. In this paper, we analyse a complex IF sub-THz receiver architecture aimed for splitting a multiGHz baseband signal into narrower sub-bands for easier A/D conversion. The architecture consists of a normal IQ direct downconversion, followed by complex mixers to center the chosen sub-carriers to DC. Image rejection versus mismatch errors is calculated both analytically and on system and circuit-level simulations. It was seen that the image rejection is dominated by the IQ downconversion stage. It is demonstrated that the mismatches in the IQ stage can be corrected digitally by weighted summing of the digital sub-bands.

This paper demonstrates the design and implementation of an inductorless analog band-pass filter (BPF). Band-pass filters are widely used in communication systems, wireless transceivers and audio systems, they only pass signals within a desired frequency range. The principles mentioned in this article can be generalized to design any analog filter regardless of its order, approximation and prototype. The design procedure can be broken down into three main parts, first of all, a passive low-pass filter (LPF) is implemented, then the passive LPF is converted into a passive BPF. Finally, the passive BPF is transformed into an active BPF by adding operational amplifiers. The active BPF is then modified into two different topologies, the first in which the inductors are replaced with simulated- inductors (gyrators), while in the second topology, less operational amplifiers are used.

This work explains the process of designing and synthesizing a MOD 13 binary down counter using 180 nm CMOS technology transistors. The beginning of the count is a combination of 1110(2), the end of the count is 0010(2). Simulations are made at the circuit level (transient analysis) to verify that the circuit functions correctly, then the integrated circuit layout is prepared by connecting the components manually. Finally, the layout is simulated to see how the existence of parasitic resistances and capacitances affect the output signals and it is used to estimate the maximum allowable clock frequency (fclk).

The given work is devoted to designing and implementing different dynamic offset cancellation techniques for 50 nm technology CMOS operational amplifiers. The goal is to minimize or get rid of the effects of the offset voltage. Offset voltage exists in all differential amplifiers due to the fact that no pair of transistors can be fabricated with the same size, there is always a slight difference in their dimensions (length or width), this gives rise to an undesirable effect called offset, the value of offset voltage for cheap commercial amplifiers are in the range of 1 to 10 mV, de-spite the fact that this isn’t a significant value, due to the high gain of such amplifiers, this voltage is amplified by tens or hundreds of times, this results in clipping of the output signal and this further limits the amplifier’s maximum allowable input voltage within the given dynamic range, hence its of great importance to take this small voltage into consideration, low-offset amplifiers find applications in mixers, analog to digital converters, instrumentation devices, etc. In this thesis, by using two different techniques for removing offset voltage (chopping and auto-zeroing), five low offset operational amplifiers were designed. The implemented methods reduced the flicker noise by more than 457 times (from 9.4 nV/√Hz to 20 pV/√Hz) at 1 Hz. All the simulations were done using Cadence Virtuoso.