This paper presents a comprehensive overview of 28 nm high-k-metal gate-based ferroelectric field effect transistor devices for synaptic applications. The device under test was fabricated on 300mm wafers at GlobalFoundries. The fabricated devices demonstrate 103 WRITE-endurance cycles and 104 seconds of data-retention capability at 85°C. We have also assessed the FeFET-based crossbar array’s performance in system-level applications. By simulating the FeFET crossbar array for neuromorphic applications, the system performance was assessed. For datasets from the National Institute of Standards and Technology (MNIST), the crossbar array achieved software-comparable inference accuracy of about 97% using multilayer perceptron (MLP) neural networks.

Hafnium oxide (HfO2)-based ferroelectric field effect transistors (FeFETs) have revolutionized the emerging non-volatile memory area, especially with the potential to replace flash memories for several applications. In this article, we investigate the suitability of FeFETs memories, especially FeFET-based content addressable memory (CAM)-cells, as storage class memory under junction temperature variations. FeFETs with silicon oxynitride interfacial layer have been fabricated and characterized at various temperatures, varying from room temperature to 120◦C. Although the memory window, numbers of programmable states, and endurance deteriorate at high temperatures, FeFETs show excellent robustness in data retention, write latency, and read stability at all temperatures, especially for binary operation. Finally, system SPICE simulations using experimental data were conducted to gauge the robustness of the data-search operation using the CAM array under different temperatures. Despite temperature-variation-induced changes in FeFET devices, we have observed that binary CAM cells perform robust and unerring search operations for storing and searching data at temperatures up to 120 °C.

In this study, we present CIMulator, a simulation platform for crossbar arrays based on synaptic element types such as resistive random access memory (RRAM), ferroelectric field-effect transistor (FeFET), and phase change memory (PCM) devices. We have developed a custom-made synapse model for FeFET and adopted non-linear weight update expressions for RRAM and PCM to study the non-ideal behaviors and device variations extensively. To reduce the required distinguishable conductance levels of the devices, advanced methods such as the accumulated weight update method and novel architectures such as 1D1S were employed, resulting in great results with reduced efforts. However, this methodology may not be advantageous for all synaptic devices and at all times. Therefore, we present the most viable neural network solution based on device characteristics. Our results demonstrate that the proposed simulation platform can effectively model analog synaptic devices and provide insight into their non-ideal behaviors and device variations, contributing to the development of efficient and highperformance neuromorphic computing systems.

The versatility of hafnium oxide-based ferroelectric memories to function as a storage class memory, a synaptic device for neuromorphic implementation, and a device capable of high-density integration have made them attractive candidates for next-generation technology. Ferroelectric memories have been increasingly popular with the discovery of ferroelectricity in hafnium oxide at a shallow thickness and compatibility with complementary metal-oxide-semiconductor-compatible processes. The single transistor-based ferroelectric cell makes them ideal for non-volatile embedded memory solutions, bridging the gap between on-chip SRAM and external data storage (e.g. Flash). This paper begins with discovering ferroelectricity in Rochelle salt and discusses the neoteric progress up to successful integration with 3D memory.

In this study, ferroelectric field-effect-transistors (FeFETs) with nitride (SiON) interface having various gate lengths (LG) and gate widths (WG) were investigated to study the influence of gate dimensions on the memory window (MW) and endurance characteristics of the FeFETs. The experimental results show the MW of FeFET increases with decreasing LG and increasing of WG due to the increased fringe effect of the metal gate electrode from parasitic fringing capacitance. Thus, in the design of FeFET, fringe effect must be considered carefully. However, no considerable impact was observed on endurance characteristics of the FeFETs as the gate dimensions were varied.

This letter proposes a memory cell, denoted by 1F-1T, consisting of a ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET, denoted by 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and the experimental data is used to model and simulate single-cell and memory arrays. The simulation shows significant improvement in bit-line (BL) current (IBL ) variation for 1F-1T memory array. Finally, the system-level neuromorphic simulation with 1F-1T synapses shows an inference accuracy of 97.6% for MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

Instigated by the plethora of data generated by edge devices and IoT devices, machine learning has become the de facto choice of everyone for solving many tasks. Applications such as intelligent healthcare monitoring systems, smart watches, or automatic cars require real-time processing of the data or image, which is done by machine learning algorithms with higher efficiency than humans. There are two possible methods for artificial intelligence?1. non-von-Neumann hardware-based implementation of neural networks 2. traditional computer science based approach for neural networks or traditional von-Neumann architecture?based implementation of neural networks The standard von-Neumann performance of neural networks, where the memory and computation parts are segregated, suffers from severe latency with increasing number of edge devices. However, the multitude of edge devices used in our daily life imposes strict restrictions on latency, device area, and power consumption for hardware. Therefore, we need to take the route beyond the CMOS-based mixed-signal implementation of neural networks, where the memory bandwidth is not limited by the quintessential von-Neumann archi?tecture. The primary motivation of present-day research on the non-von-Neumann computing architecture is to build dedicated hardware modules for implementing low-power, fast-computing units without affecting the recent trend of scaling. This chapter focuses on amorphous indium-gallium-zinc-oxide (α-IGZO) based and their system-level applications. Back-end-of-line (BEoL) compatible indium IGZO based multibit one-time programmable (OTP) ferroelectric thin film transistors (FeTFT) with lifelong retention capability were fabricated. The maximum temperature of the entire fabrication process was limited to 350oC. The gate-stack engineering by varying the thickness ratio of ferroelectric hafnium zirconium oxide (HZO) and IGZO layer fomented excellent data-retention capability and one time programming property. Further, we have evaluated the performance of IGZO-based FeTFT as synaptic devices for an inference engine. The system-level simulation revealed inference accuracy loss of only 1.5% after ten years without re-training for Modified National Institute of Standards and Technology (MNIST) hand-written digits in a multi-layer perceptron (MLP) neural network with a baseline of 97%. The proposed inference engine also showed superior energy efficiency and cell area of 95.33 TOPS/W (binary) and 8F2 , respectively.

CMOS compatibility and the low process temperature of hafnium oxide(HfO2) make HfO2-based ferroelectric FETs an excellent candidate for logic, memory, and neuromorphic devices. This article discusses the challenges and opportunities of using hafnium oxide-basedferroelectric memory for in-memory-computing applications. Finally, we try to draw the roadmap for them.

Interfacial Layer Engineering to Enhance Endurance and Noise Immunity of FeFETs for IMC Applications

This paper reports high precision, highly linear MAC operation conducted on 28nm ferroelectric (Fe) FET (FeFET) based 4Kb computing-in-memory (CIM) core with 1FeFET-1T structure. The CIM-macro consists of 4 Kbit ultra-high precision FeFET based synaptic core, ADCs, and peripheral components for data processing. The crossbar array in the synaptic core was divided into 8×8 tiles for minimizing the voltage swing variations across word-line (WL), source-line (SL) and bit-line (BL). The FeFET-based macro achieved software-comparable inference accuracy for LeNET-5 and VGG-16 networks for MNIST and CIFAR-10 datasets.

This paper reports back-end-of-line (BEoL) compatible indium gallium zinc oxide (IGZO) based multibit one-time programmable (OTP) ferroelectric thin-film transistors (FeTFT) with lifelong retention capability. The maximum temperature of the entire fabrication process was limited to 350oC. The gate-stack engineering by varying the thickness ratio of hafnium zirconium oxide (HZO) and IGZO layer fomented data-retention capability over ten years and OTP property. Further, we have evaluated the performance of IGZO-based OTP FeTFT as synaptic devices for an inference engine. The system-level simulation revealed inference accuracy loss of only 1.5% after ten years without re-training for Modified National Institute of Standards and Technology (MNIST) hand-written digits in a multi-layer perceptron (MLP) neural network with a baseline of 97%. The proposed inference engine also showed superior energy efficiency and cell area of 95.33 TOPS/W (binary) and 8F2, respectively.