The von Neumann bottleneck has restricted further advancement in processors in terms of speed. To overcome this several brain-inspired computing paradigms such as in-memory and hyperdimensional computing are being explored. The different architectures available for hyperdimensional computing uses Boolean operations of xor and majority repeatedly at different levels. However, the latency associated with fetching of data from associative memory to processing units repeatedly can make such systems slow. This can be overcome by placing the associative memory and the processing logic gates together at various stages of operation, resulting in in-memory hyperdimensional computing. However, this results in use of thousands of logic gates making such systems highly resource intensive. Thus, an energy and area-efficient in-memory implementation of xor and majority logic becomes crucial for deployment of hyperdimensional computing accelerators in latency and resourceconstrained applications. FeFETs are a class of emerging nonvolatile memory with various desirable properties. Proposing of in-memory xor and majority gates in FeFET arrays can enable deployment of efficient in-memory hyperdimensional computing. In this work, for the first time we have developed a 1 transistor xor and majority gate using FDSOI FeFET. The proposed gates only consumes footprint of 0.07 µm 2. We have also demonstrated spam-filtering operation on SMS data set using N-gram encodingbased HD computing architecture with an accuracy of 91.38%. The variation of spam-filtering accuracy with dimension of the hypervectors and window width of the N-gram-based encoder was also studied for spam filtering operation for the first time.

Probabilistic/stochastic computations form the backbone of autonomous systems and classifiers. Recently, biomedical applications of probabilistic computing such as hyperdimensional computing for DNA sequencing, Bayesian networks for disease diagnosis, etc. have attracted significant attention owing to their high energy efficiency. Bayesian inference is  widely used for decision making based on independent (often conflicting) sources of information/evidence. A cascaded chain or tree structure of asynchronous circuit elements known as Muller C-Elements can effectively implement Bayesian inference. Such circuits utilize stochastic bit streams to encode input probabilities which enhances their robustness and fault tolerance. However, the CMOS implementation of Muller C-Element are bulky and energy hungry which restricts their widespread application in resource constrained IoT and mobile devices. To enable Bayesian inference based decision making in IoT devices such as UAVs, robots, space rovers, etc, for the first time, we propose a highly compact and energy-efficient implementation of Muller C-Element utilizing a single Ferroelectric FET. The proposed implementation exploits the unique drain-erase, program inhibit and drain inhibit characteristics of FeFETs to encode the output as the polarization state of the ferroelectric layer. Our extensive investigation utilizing an in-house developed experimentally calibrated compact model of FeFET reveals that the proposed C-Element consumes an ultra-low power of 1.07 fW. We also propose a novel read circuitry for realising a Bayesian inference engine by cascading a network of proposed FeFET based C-Elements for practical applications. Furthermore, for the first time, we analyze the impact of cross-correlation between the stochastic input bit streams on the accuracy of the C-Element based Bayesian inference implementations. For proof of concept demonstration, we utilize the proposed FeFET based Muller C-Element for performing breast cancer diagnosis utilizing Wisconsin data-set.

A novel technique to develop a smart cap is proposed, to help blind and visually impaired people in perceiving there environment. It is cheap, light weight and immune to signal fluctuations.