In this paper, a novel reconfigurable 5.8 GHz linear power amplifier with a digital pulse-shaping filter (PSF) to improve the spurious is presented for dedicated short-range communication (DSRC) transceivers. An on-chip reconfigurable load transfer network (LTN) is able to match the output load variations to PA while keeping output return loss blow -10 dB. Furthermore, LTN improves the stability by varying quality factor of LTN for different operation conditions. The power amplifier consists of a Class-AB driver stage and a cascode topology for the PA core. To improve the spurious of the PA and controlling modulation index a gaussian-based digital pulseshaping filter is implemented which has achieved an occupied bandwidth (OCB) of less than 2 MHz. Realized in a 0.13-m CMOS technology with an area of 1.1 mm2, the power amplifier achieves 10 dBm and 25 dB output power and dynamic range, respectively. PA dissipates 76 mA from 3-V supply voltage.

In this paper, a 5.8 GHz linear power amplifier (PA) in a 130 nm CMOS process using transconductance linearization technique is presented. The power stage consists of a main amplifier with Class-F load impedance and two auxiliary amplifiers which are biased for weak Class-AB. The proposed configuration increases both the linearity of the PA at high output power levels and the efficiency at back-off powers. The AM-AM and AM-PM nonlinearities of the auxiliary amplifiers cancel the same nonlinearities of the main amplifier at higher output powers. A bypass network is introduced to prevent a positive feedback and common-mode oscillations through the supply path. The PA shows a saturated output power of 23 dBm with 41% PAE and 17dB small-signal gain. Dynamic supply voltage allows a low-power operation with improved efficiency for back-off input powers. For supply voltages of 1.8V, 2.2V, and 3.3V the linear output power and PAE are 12.67dBm, 16.77dBm, and 18.1dBm and 11%, 19.27%, and 20.44%.