This paper proposes the design and implementation of a CNTFET-based Ternary Logic processor. The processors' fundamental blocks like the instruction fetch, register file, data memory, and control unit designs are also presented. HSPICE simulation for the processor using a standard CNTFET model is performed and its functionality is verified using a few benchmark programs.

This paper presents three new power-efficient designs of ternarySRAM using carbon-nanotube-field-effect transistors (CNTFETs). Two of the proposed ternary SRAM designs are cycle-operator based and the third design is buffer-based.