As machine learning continues to find applications, extensive research is currently underway across various domains. This study examines the current methodologies of machine learning being investigated to optimize semiconductor manufacturing processes. Our research involved searching the SPIE Digital Library, IEEE Xplore, and ArXiv databases, identifying 58 publications in the field of machine learning-based semiconductor process optimization. These investigations employ machine learning techniques such as feature extraction, feature selection, neural network architecture, and are analyzed using different algorithms. These models find applications in advanced process control, virtual metrology, and quality control, critical aspects in semiconductor manufacturing for enhancing throughput and reducing production costs. We categorize the papers based on the methods and applications employed, summarizing the primary findings. Furthermore, we discuss the general conclusions of several studies. Overall, the reviewed literature suggests that machine learning-based semiconductor manufacturing is rapidly gaining popularity and advancing at a swift pace.

Neural networks have been commonly used in different domains. Hardware implementation of the neural networks is challenging to fit different applications’ requirements. This often necessitates realizing different neural network FPGA configurations from the very scratch specific to a given application. This paper proposes a flexible method that can be reconfigured in a self-supervised way to fit several ap?plications’ requirements, by providing only maximum available computational nodes a prior. The proposed method is based on reconfiguring the required number of hidden layers and hidden nodes of that layer based on a given application. Reconfigurability also allows to decide and update the number of active nodes, at layer (l+1), which receives computational results of l th layer nodes. A configuration block is used to send a signal to the control block which follows each node output. The control block decides which following nodes receive the output according to the corresponding signal value from the configuration block. Each node receives a signal to be enabled or disabled from the configuration block. Therefore, the number of inputs of each node and nodes in each layer is determined according to the desired performance. The goal here is to automatically propose the optimal NN configuration through reconfigurability to fit different applications, to achieve the maximum accuracy possible. The optimality can be demonstrated in terms of minimum average power, average delay, and area overhead as well as maximum throughput and accuracy. The main advantage of the proposed approach is the reusability of the optimized architecture (which is self-learned online) for the very first application/dataset, as the initial configuration for any new/next dataset/application rather than starting from scratch. We have demonstrated with experimental results, the proposed approach helps primarily to significantly reduce optimized architecture search cost (the number of online training iterations) as well as associated average power consumption for successive datasets/applications. Our proposed method demonstrates its effectiveness both quantitatively and qualitatively. The proposed method is verified against two different classification problems, MNIST and CIFAR-10. Our proposed reconfigurable method demonstrates stable accuracy of 98.97% and 98.95% against the state-of-the-art neural network with two different fixed configurations as (98.85% and 73.0%) for MNIST and (93.47% and 70.21%) for CIFAR-10, respectively. The proposed method also demonstrates a 20.9% reduction in average power dissipation against the state-of-the-art method. The proposed method is implemented and tested using VHDL and Altera FPGA. The results show resource utilization is comparable with the state-of-the-art method.

As semiconductor manufacturing is moving towards 3 nm nodes and beyond, the development of advanced metrology techniques to control the quality of fabricated features on silicon wafers is becoming more and more crucial. Among the popular metrology methods, Scanning Electron Microscopy is one of the most important techniques since it can produce images with resolutions as low as a few nanometers. Thus, SEM is very suitable to inspect the critical dimension of nanoscale printed structures. However, CD-SEM images intrinsically contain a significant amount of background noise due to various sources. This background noise can lead to inaccurate metrology and erroneous defect detection. There is a significant requisite to reduce the noise signal in CD-SEM images while keeping the actual morphology of the pattern feature unaltered. In this paper, we proposed two deep learning-based methods to denoise SEM images, one based on (1) supervised/semi-supervised learning technique, and the other based on (2) unsupervised learning. The two proposed methods were experimented with different noisy SEM images of categorically different geometrical patterns and have demonstrated exceptional performance in reducing noise both qualitatively and quantitatively. We also have demonstrated how our proposed deep learning denoiser is applicable towards challenging application scenarios such as defect inspection and contour extraction, specifically with thin resists, with significantly improved accuracy. First, we have validated that our proposed denoising techniques, especially the unsupervised model, are effective. The unsupervised training scheme also requires single noisy acquisitions to train denoising CNNs without any ground-truth or synthetic images, against previous supervised/semi-supervised data greedy approaches. Second, the proposed deep learning denoiser assisted framework allows improved defect inspection and contour extraction with thin resists. The goal of this work is to establish a robust de-noising technique to reduce the dependency of SEM image acquisition settings and to extract repeatable and accurate CDSEM metrology information for high NA EUV. Finally, the limitations of our proposed approaches and how to overcome them were also thoroughly discussed.