The risk of cascading failures in power electronic systems is mitigated by detecting damaged semiconductor devices before energizing power circuits. Existing fault diagnostic approaches require the energization of the power circuit and/or specialized sensing and conditioning arrangements. In this paper, a technique to detect faulty MOSFET switching cells, prior to power-loop energization and using no additional hardware, is proposed. The proposed method exploits a gate driver-induced residual voltage (GIRV), appearing across the de-energized DC terminals of a switching cell, to distinguish between healthy and damaged cells and thus, identify failures. To quantify the GIRV, the operation of a de-energized switching cell is analyzed in the time domain. Short-circuit, open-circuit, and gate failure conditions are then analyzed and the implementation of the GIRV-based failure detection scheme outlined. The proposed scheme can be implemented using only the MOSFET gate drivers and a DC bus voltage sensor. The analysis of the GIRV is verified in circuit simulations and experiments. Further, the proposed failure detection scheme is experimentally validated on existing hardware by modifying the software start-up routines.

The LCC resonant converter with a capacitive output filter is a popular topology for variable load applications, though the simultaneous design requirements of wide load range, soft switching, and low conduction loss are not clearly tackled in available design strategies. In this paper, the existing time-domain analysis of the converter is extended in a normalized design-oriented fashion. The proposed extension to boundary modes lends itself to the derivation of critical converter characteristics such as the soft switching range. A dimensionless converter and load characteristic-based design algorithm with parameter decoupling is developed to meet the load requirements. The design algorithm reduces converter rms current while meeting practical requirements of zero voltage switching and constraints on switching frequency across the load range. The proposed design method is validated using circuit simulations incorporating series dissipative non-idealities and the transformer magnetizing inductance, and also on a 160 W laboratory prototype with switching frequency within the designated limits and $>$96$\%$ experimental efficiency.

Switching frequency is utilized as a degree of freedom in digital control strategies for power converters. In addition to carrier-based schemes, quadrature oscillators offer an alternative method for the generation of variable frequency switching pulses. In this paper, amplitude instability in a computationally simple digital quadrature oscillator is analyzed. Algorithms for stabilizing the oscillator are developed based on this. Further implementation issues arising are addressed and a systematic comparison to carrier-based schemes is executed. It is shown that the proposed approach can be implemented with only 4 additions and 4 comparison steps without resorting to multiplication. The studies are validated in system simulation and experiments on a commercial FPGA board.