The new trend in large area noble liquid experiments is to measure the scintillation light with photodetectors and their electronics inside the active volume. Compared to the typical approach of using silicon photomultipliers (SiPM) with the analog readout chain to an analog-todigital converter, this paper presents a new 3D photon-to-digital converter (PDC) readout that takes advantage of the binary nature of the single-photon avalanche diode. The readout contains 4096 pixels over 25 mm 2 , each including a 3D bonding pad and a quenching circuit. The readout features three different outputs : a fast flag to get the timestamp of each event from an external time-to-digital converter, a digital sum to retrieve the number of pixels triggered during an event and an analog monitor to generate an analog SiPM-like output. The analog monitor is also used to validate the two former digital outputs. The readout also includes 61 2D CMOS SPADs for validation purpose prior to the final 3D integration with a Teledyne DALSA custom SPAD array. As a first system integration toward large-area detector applications, a mini-tile of 2 × 2 readouts has been developed to test all the functionalities. The measured single-photon timing resolution ranges from 72 to 93 ps FWHM across the mini-tile SPAD channels population (i.e. 4 × 61 channels). The flag timing resolution is below 95 ps RMS, which includes the contribution of the optimized flag H-tree with an additional trigger tree to replace the 3D SPAD array for 2D testing. Once bonded with the 3D SPADs, the trigger tree won't be required to measure the flag timing resolution. With the removed contribution of the trigger tree, the estimated flag timing resolution should be below 45 ps RMS. The benefits of the digital sum output depend on the application, and this paper focuses on two cases. First, a low-power coincidence scheme for the nEXO liquid xenon experiment, leading to a power consumption as low as 140 µW per PDC. On the other hand, with a finer sampling mode of the scintillation light for pulse shape discrimination in liquid argon, the power consumption remains below 100 µW per PDC. Overall, this readout is designed as a replacement for a typical analog SiPM chain, without any compromise on the performances.

When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.