This paper presents novel observations on the impact of ground-bounce noise (GBN) on Logic-HIGH levels of the output response of CMOS inverter circuits. While the impact of power supply noise on Logic-HIGH is very obvious as well as comprehensively studied in the literature, the impact of ground bounce is perceived and the analysis is majorly focused on logic-LOW. This work demonstrates the significant impact of GBN on Logic-HIGH and the observations are supported by a theoretical analysis using a semi-analytical approach. Several examples are considered to validate the novel observations considering both simulation as well as measurement-based case studies. The simulation based case studies are performed using a 40 nm technology of United Microelectronics Corporation (UMC), and measurement based case studies are performed using standard HEX inverter Integrated Circuits (ICs). There is a close correlation observed between the practical observations and its theoretical foundation.