This paper presents a new method to characterize the linearity of on-chip filters, considering the interaction between cascaded blocks. Unlike conventional methods, this approach uses only one buffer, simplifying the design and improving accuracy. This method accurately extracts the filter's transfer function in both its bandpass and stopband. The filter and buffer are designed using GlobalFoundries 22nm FDX technology, incorporating a back-gate biasing tuning mechanism in the buffer design. Results show a variation of ≈ 0.17 V and ≈ 0.19 V in the threshold voltage of PMOS and NMOS devices, respectively, for |1.2 V | shift in their back-gate voltage, aiming to maintain the performance of the buffer under process variation. The post-layout simulations demonstrate that the new method achieves a filter linearity of IIP 3 = 10.46 dBm, with an accuracy of 99.4% compared to the standalone filter's linearity. Similar consistency is observed across various process corners.