Reference spurs are generated at the spectral output of conventional phase-locked loops (PLLs) due to nonidealities of the phase-frequency detector (PFD) and the charge pump (CP). The nonidealities are mathematically modeled by time-domain approximation of the PLL control voltage and compared with simulated values which match with fair accuracy. In this work, some modifications are proposed to the PFD and the CP to reduce the spurs. The spur magnitudes are further reduced by adding a sampler at the output of the loop filter, with no significant changes to the PLL characteristics (except phase margin). A PLL operating at 8-GHz is used to demonstrate the effects of the proposed modifications on the spur magnitudes. Simulations are carried out in 28nm CMOS technology.

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The sensitivity and dynamic range of a differential ring oscillator-based capacitance measurement interface has been enhanced using a frequency domain capacitance-to-voltage measurement technique. This is followed by the noise-immune detection of phase/frequency, caused by a change in the sensor capacitance. A single current source based charge-pump (CP) is proposed, which mitigates the impact of current mismatch on the output voltage. The proposed design is fabricated in a 130 nm CMOS technology with an active area of 0.17 mm 2. It exhibits a maximum sensitivity of 244.8 mV/fF. The sensor operation in three capacitance ranges at different sensitivities was demonstrated by measuring digitally tuned on-chip and offchip capacitances. Experimental results show that the proposed design achieves a capacitance resolution of 13 aF, with a 10 pF nominal sensor capacitance, using an 8-bit ADC, with a measurement time of 60 µs while consuming 0.7 mW from a 1.2 V supply. Compared to prior work with similar performance, this represents a significant improvement in the measurement time and reusablity of the circuit for different applications.