Charge pump-based (CPB) dynamic biasing can be exploited in latched comparators to optimize the speed-noise tradeoff allowing operation at low supply voltage with high speed and low noise. In this work we provide the theoretical foundation for this optimization, and present two single-stage comparator topologies operating at 0.6 V supply. The former exploits dynamic biasing to achieve a delay of 95 ps with low power consumption and low noise, whereas the latter exploits a pseudo-differential approach to allow offset calibration with minimal overhead, at the cost of higher noise. Simulations in 28-nm CMOS validate the proposed model and show that the proposed topologies are able to achieve state-of-the-art performance.