Without a low-cost, highly efficient power conversion circuit system, the current achievements in Information and Communication Technology would not have been possible. The integration of power conversion circuit systems began with data writing for non-volatile semiconductor memories. Utilizing a switched-capacitor converter has enabled full integration due to its configuration of switch, capacitor, oscillator, and regulator components. With the scaling of CMOS technology, the supply voltage for LSIs has started to decrease. The voltage drop across switches has relatively increased, resulting in escalating costs and power losses. To address this, a shift from passive switches to active ones has been made to mitigate voltage drops and ensure scalability. Reconfigurability has been developed to maintain low cost and high power-efficiency even in applications with significant fluctuations in voltage conversion ratios. On the other hand, digital circuits used to operate on power supplies downscaled inefficiently by linear regulators. As the integration density of digital circuits reached the power density limits, more efficient switched-capacitor voltage-down converters have become prevalent to enhance power efficiency. Nowadays, power supply voltages and clock frequencies are adjusted dynamically based on computational loads. Thus, reconfigurability remains crucial even in switched-capacitor voltage-down converters due to demands for variable voltage conversion ratios. In this article, we explore the evolution of reconfigurable switched-capacitor converters, tracing their development from the rich history of switched-capacitor converters spanning over a century.

In this paper, we propose an address-dependent divided-bit-line (BL) NAND Flash memory for reduction in read latency. Energy in bit-line path can be also reduced with this design. A single switching MOSFET is added per BL. When a memory cell located closer to the sense amplifier is selected for read, the switch gets turned off. The sense amplifier sees shorter BL with smaller parasitic capacitance and resistance, resulting in lower latency and energy in BL path. When a memory cell located farther from the sense amplifier is selected for read, the switch gets turned on. The sense amplifier sees the original bit-line when the on-resistance of the switch is sufficiently low in comparison with the BL resistance. The averaged BL access time and energy can be minimized analytically when the switch is placed at xSW of 0.58 and 0.50, respectively, where xSW indicates the switch location (xSW = 0 at the closest to the sense amplifier and xSW = 1 at the farthest from the sense amplifier), assuming that the memory cells are accessed in random. With the proposed design, the average read latency and energy can be reduced to 62 % and 75 %, respectively. The effectiveness of the proposed design was validated with SPICE. This paper also investigates 1) the case where hot memory cells are placed in the closer side whereas cold cells are in the farther side and 2) the case where more switches are built in every BL. In this paper, NAND Flash memory is considered to quantifying the effectiveness of the proposed design on read latency and energy.