In this article, for the first time, we present a comprehensive study of the impact of cryogenic temperatures on the minimum-operating voltage (V min) of 5 nm Fin Field-Effect Transistors (FinFETs)-based Static Random-Access Memory (SRAM) cells. To develop the SRAM V min evaluation framework, we have measured the FinFETs fabricated using a commercial 5 nm FinFET technology down to 10 K. Next, we calibrate a cryogenic aware BSIM-CMG FinFET compact model, which we use to perform the V min characterization. For a comprehensive study, we evaluate three industry-standard SRAM cell types-(i) high-density cell (HDC), (ii) low-voltage cell (LVC), and (iii) highperformance cell (HPC). We analyze the impact of the threshold voltage (VTH) and Gate Length (L G)-only variations on the SRAM noise resilience. At cryogenic temperatures minimum-read voltage (V min,R) = 0.15 V (62 % decrease from room temperature) and minimum-write voltage (V min,W) = 0.45 V is achieved without read/write assist circuits. We also highlight that the LVC cell provides the best trade-off for V min between read and write operations for low-power cryogenic applications.