Efficient processing of large data volumes at low power is a critical challenge in modern computing systems. Spiking Neural Networks (SNNs), inspired by biological spikebased communication, offer a promising solution through energyefficient neuromorphic architectures. Unlike traditional neural networks, SNNs utilize spike-timing-dependent plasticity (STDP) learning, reducing computational complexity and power consumption. Prior implementations often rely on external computational platforms or memristive devices, which introduce fabrication and integration challenges. This work presents the design and implementation of an on-chip SNN architecture using SCL 180nm CMOS technology. The architecture features Leaky Integrate-and-Fire (LIF) neurons and a memristive synapse circuit that incorporates STDP learning for efficient pattern recognition. Optimizations, such as removing current mirrors and reset logic in the neuron circuit, minimize area and power requirements. A Verilog-A designed summing amplifier processes synaptic outputs, while a Winner-Takes-All mechanism ensures accurate classification of input patterns, including characters and directional signs. The single-layer network demonstrates lowlatency performance and high efficiency in recognizing simple patterns. Simulation results validate the robustness of the architecture, paving the way for future enhancements to include hidden layers for handling complex patterns and integrating advanced technologies to expand the scope of neuromorphic computing applications.

Domino logic circuits inherent speed and area efficiency benefits make them essential for high-speed and low-power digital applications. However, particularly in contemporary, massively scaled technologies, traditional domino logic architectures typically encounter issues such as excessive power waste, higher delay, and lower noise immunity. To overcome these constraints, we suggest two to three improved circuit designs that offer new designs on traditional domino logic. To meet the demands of diverse high-performance applications, each design concentrates on certain performance improvements, such as lowering power consumption, enhancing noise margins, or optimizing delay characteristics. The newly designed domino circuits presented in this work are carefully examined and contrasted with traditional domino logic in several performance parameters. Important features including noise margin, area efficiency, power-delay product (PDP), and process variability tolerance are all included in a thorough comparison table. According to simulation data in ideal conditions, the suggested circuits perform better than conventional domino designs in controlled environments, showing notable gains in speed, delay, and energy while preserving a high level of operational reliability. The results of our study demonstrate how domino logic circuits can improve the performance of high-speed digital systems. The proposed designs give practical solutions to some of the fundamental difficulties we face in existing domino logic such as power and delay.